SH7032 Datasheet, PDF (216/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 9 Direct Memory Access Controller (DMAC)
The DE bit is initialized to 0 by a reset and in standby mode.
Bit 0: DE
0
1
Description
DMA transfer disabled
DMA transfer enabled
(Initial value)
9.2.5 DMA Operation Register (DMAOR)
The DMA operation register (DMAOR) is a 16-bit read/write register that controls the DMA
transfer mode. It also indicates the DMA transfer status. It is initialized to H'0000 by a reset and in
standby mode.
Bit
Initial value
Read/Write
15
14
13
12
11
10
9
8
——
—
—
—
—
—
PR1
PR0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R/W R/W
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
AE
NMIF DME
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R/(W)* R/(W)* R/W
Note: * Write only 0 to clear the flag.
Bits 15–10—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 9 and 8—Priority Mode Bits 1 and 0 (PR1 and PR0): PR1 and PR0 select the priority level
between channels when there are simultaneous transfer requests for multiple channels.
Bit 9: PR1
0
0
1
1
Bit 8: PR0
0
1
0
1
Description
Fixed priority order (Ch. 0 > Ch. 3 > Ch. 2 > Ch. 1) (Initial value)
Fixed priority order (Ch. 1 > Ch. 3 > Ch. 2 > Ch. 0)
Round-robin mode priority order (the priority order immediately after a
reset is Ch. 0 > Ch. 3 > Ch. 2 > Ch. 1)
External-pin round-robin mode priority order (the priority order
immediately after a reset is Ch. 3 > Ch. 2 > Ch. 1 > Ch. 0)
Bits 7–3—Reserved: These bits are always read as 0. The write value should always be 0.
Rev. 7.00 Jan 31, 2006 page 190 of 658
REJ09B0272-0700