SH7032 Datasheet, PDF (78/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 4 Exception Handling
Exception
source
Reset
Address
error
Interrupt
Instruction
• Power-on reset
• Manual reset
• CPU address error
• DMA address error
• NMI
• User break
• IRQ
• On-chip module
• Trap instruction
• General illegal
instruction
• Illegal slot
instruction
Priority
High
• IRQ0–IRQ7
• Direct memory access
controller
• 16-bit integrated timer
pulse unit
• Serial communication
interface
• Parity control unit
(part of the bus con-
troller)
• A/D converter
• Watchdog timer
• DRAM refresh control
unit (part of the bus
controller)
• TRAPA instruction
• Undefined code
• Undefined instruction
or instruction that
rewrites the PC^*1
placed directly after ^Low
a delayed branch
instruction^*2
Notes: 1. The instructions that rewrite the PC are JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, and
TRAPA.
2. The delayed branch instructions are JMP, JSR. BRA. BSR, RTS, and RTE.
Figure 4.1 Exception Source Types and Priority
Rev. 7.00 Jan 31, 2006 page 52 of 658
REJ09BX0272-0700