SH7032 Datasheet, PDF (87/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 4 Exception Handling
4.5 Instruction Exceptions
4.5.1 Types of Instruction Exceptions
Table 4.8 shows the three types of instruction that start exception handling (trap instructions,
illegal slot instructions, and general illegal instructions).
Table 4.8 Types of Instruction Exceptions
Type
Trap instruction
Illegal slot
instruction
General illegal
instructions
Source Instruction
TRAPA
Undefined code or instruction
that rewrites the PC located
immediately after a delayed
branch instruction (delay slot)
Undefined code in other than
delay slot
Comments
—
Delayed branch instructions are: JMP, JSR,
BRA, BSR, RTS, RTE. Instructions that
rewrite the PC are: JMP, JSR, BRA, BSR,
RTS, RTE, BT, BF, and TRAPA
—
4.5.2 Trap Instruction
Trap instruction exception handling is carried out when a trap instruction (TRAPA) is executed.
The CPU then:
1. Saves the status register by pushing register contents onto the stack.
2. Pushes the program counter value onto the stack. The PC value saved is the start address of the
next instruction after the TRAPA instruction.
3. Reads the exception handling routine start address from the vector table corresponding to the
vector number specified in the TRAPA instruction, branches to that address, and starts
program execution. The branch is not a delayed branch.
Rev. 7.00 Jan 31, 2006 page 61 of 658
REJ09B0272-0700