SH7032 Datasheet, PDF (351/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 11 Programmable Timing Pattern Controller (TPC)
Bits 1 and 0—Group 0 Compare Match Select 1 and 0 (G0CMS1 and G0CMS0): G0CMS1
and G0CMS0 select the ITU channel that triggers TPC output group 0 (TP3–TP0).
Bit 1:
G0CMS1
0
Bit 0:
G0CMS0
0
1
1
0
1
Description
TPC output group 0 (TP3–TP0) output is triggered by compare match in
ITU channel 0
TPC output group 0 (TP3–TP0) output is triggered by compare match in
ITU channel 1
TPC output group 0 (TP3–TP0) output is triggered by compare match in
ITU channel 2
TPC output group 0 (TP3–TP0) output is triggered by compare match in
ITU channel 3
(Initial value)
11.2.8 TPC Output Mode Register (TPMR)
TPMR is an eight-bit read/write register that selects between the TPC’s ordinary output and non-
overlap output modes in group units. During non-overlap operation, the output waveform cycle is
set in ITU general register B (GRB) for use as the output trigger and a non-overlap period is set in
general register A (GRA). The output value then changes on compare matches A and B. For
details, see section 11.3.4, TPC Output Non-Overlap Operation. TPMR is initialized to H'F0 by a
reset. It is not initialized in standby mode.
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
—
—
—
— G3NOV G2NOV G1NOV G0NOV
1
1
1
1
0
0
0
0
—
—
—
—
R/W
R/W
R/W
R/W
Bits 7–4—Reserved: These bits are always read as 1. The write value should always be 1.
Bit 3—Group 3 Non-Overlap Mode (G3NOV): G3NOV selects ordinary or non-overlap mode
for TPC output group 3 (TP15–TP12).
Bit 3: G3NOV
0
1
Description
TPC output group 3 operates normally (output value updated according to
compare match A of the ITU channel selected by TPCR)
(Initial value)
TPC output group 3 operates in non-overlap mode (1 output and 0 output can
be performed independently according to compare match A and B of the ITU
channel selected by TPCR)
Rev. 7.00 Jan 31, 2006 page 325 of 658
REJ09B0272-0700