SH7032 Datasheet, PDF (648/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix A On-Chip Supporting Module Registers
Table A.51 TCSR Bit Functions
Bit Bit Name
Value Description
7
Overflow flag (OVF)
0
No TCNT overflow in interval timer mode
(Initial value)
Clear Condition: OVF read, then 0 written in OVF
1
TCNT overflow generated in interval timer mode
6
Timer mode select (WT/IT) 0
Interval timer mode: When TCNT overflows, interval
timer interrupt (ITI) request sent to CPU (Initial value)
1
Watchdog timer mode: When TCNT overflows,
WDTOVF signal is output externally*
5
Timer enable (TME)
0
Timer disable: TCNT initialized at H'00 and count-
up halted
(Initial value)
1
Timer enable: TCNT starts counting up. When
TCNT overflows, a WDTOVF signal or interrupt is
generated
2–0 Clock select 2–0
(CKS2–CKS0)
Clock
0 0 0 φ/2 (Initial value)
0 0 1 φ/64
0 1 0 φ/128
0 1 1 φ/256
Overflow cycle (φ=20 MHz)
25.6 µs
819.2 µs
1.6 ms
3.3 ms
0 0 0 φ/512
6.6 ms
0 0 1 φ/1024
13.1 ms
0 1 0 φ/4096
52.4 ms
0 1 1 φ/8192
104.9 ms
Note: * When the RSTE bit in RSTCSR is 1, an internal reset signal is also generated
simultaneously with the WDTOVF signal when TCNT overflows in watchdog timer mode.
Rev. 7.00 Jan 31, 2006 page 622 of 658
REJ09B0272-0700