SH7032 Datasheet, PDF (193/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 8 Bus State Controller (BSC)
Table 8.12 Bus Cycle States when Accessing Address Spaces
CPU Read Cycle, DMAC Dual Mode Read Cycle, DMAC
Single Mode Memory Read/Write Cycle
Address Space
Corresponding Bits in
WCR1 and WCR2 = 0
Corresponding Bits in
WCR1 and WCR2 = 1
External memory (areas 1, 3–5, 7)
External memory (Areas 0, 2, 6;
long wait avail-able)
1 state fixed; WAIT signal
ignored
1 state + long wait state*,
WAIT signal ignored
2 states + wait states from
WAIT signal
1 state + long wait state* +
wait states from WAIT signal
DRAM space (area 1)
Column address cycle:
1 state, WAIT signal ignored
(short pitch)
Column address cycle:
2 states + wait states from
WAIT signal (long pitch)
Multiplexed I/O space (area 6)
4 states + wait states from WAIT signal
On-chip supporting module space 3 states fixed, WAIT signal ignored
(area 5)
On-chip ROM (area 0)
1 state fixed, WAIT signal ignored
On-chip RAM (area 7)
1 state fixed, WAIT signal ignored
CPU Write Cycle, DMAC Dual Mode Memory Write Cycle
(WW1 of WCR1)
Address Space
WW1 of WCR1=0
WW1 of WCR1=1
External memory (area 1)
Setting prohibited
2 states + wait state from
WAIT signal
External memory (areas 3–5, 7)
External memory (Areas
0, 2, 6; long wait available)
2 states + wait states from WAIT signal
1 state + long wait state* + wait states from WAIT signal
DRAM space (area 1)
Column address cycle:
1 state, WAIT signal
ignored (short pitch)
Column address cycle:
2 states + wait states from
WAIT signal (long pitch)
Multiplexed I/O space (area 6)
4 states + wait states from WAIT signal
On-chip peripheral module space 3 states fixed, WAIT signal ignored
(area 5)
On-chip ROM (area 0)
1 state fixed, WAIT signal ignored
On-chip RAM (area 7)
1 state fixed, WAIT signal ignored
Note: * The number of long wait states (1 to 4) is set in WCR3.
Rev. 7.00 Jan 31, 2006 page 167 of 658
REJ09B0272-0700