SH7032 Datasheet, PDF (404/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Serial Communication Interface (SCI)
Table 13.9 SMR and SCR Settings and SCI Clock Source Selection
SMR SCR Settings
SCI Transmit/Receive Clock
Mode
Bit 7: Bit 1: Bit 0:
C/A CKE1 CKE0 Clock Source SCK Pin Function*
Asynchronous 0
0
0
mode
1
Internal
SCI does not use the SCK pin
Outputs a clock with frequency
matching the bit rate
1
0
External
Inputs a clock with frequency 16
times the bit rate
1
Synchronous 1
0
0
mode
1
Internal
Outputs the serial clock
1
0
External
Inputs the serial clock
1
Note: * Select the function in combination with the pin function controller (PFC).
13.3.2 Operation in Asynchronous Mode
In asynchronous mode, each transmitted or received character begins with a start bit and ends with
a stop bit. Serial communication is synchronized one character at a time.
The transmitting and receiving sections of the SCI are independent, so full duplex communication
is possible. The transmitter and receiver are both double buffered, so data can be written and read
while transmitting and receiving are in progress, enabling continuous transmitting and receiving.
Figure 13.2 shows the general format of asynchronous serial communication. In asynchronous
serial communication, the communication line is normally held in the mark (high) state. The SCI
monitors the line and starts serial communication when the line goes to the space (low) state,
indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit
(high or low), and stop bit (high), in that order.
When receiving in asynchronous mode, the SCI synchronizes on the falling edge of the start bit.
The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate.
Receive data is latched at the center of each bit.
Rev. 7.00 Jan 31, 2006 page 378 of 658
REJ09B0272-0700