SH7032 Datasheet, PDF (58/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 2 CPU
Classifi-
cation
Logic oper-
ations
(cont)
Types
6
Operation
Code
TST
XOR
Function
Logical AND and T bit set
Exclusive OR
Shift
10
ROTL
One-bit left rotation
ROTR
One-bit right rotation
ROTCL
One-bit left rotation with T bit
ROTCR One-bit right rotation with T bit
SHAL
One-bit arithmetic left shift
SHAR
One-bit arithmetic right shift
SHLL
One-bit logical left shift
SHLLn
n-bit logical left shift
SHLR
One-bit logical right shift
SHLRn
n-bit logical right shift
Branch
7
BF
Conditional branch (T = 0)
BT
Conditional branch (T = 1)
BRA
Unconditional branch
BSR
Branch to subroutine procedure
JMP
Unconditional branch
JSR
Branch to subroutine procedure
RTS
Return from subroutine procedure
System
11
control
CLRT
CLRMAC
T bit clear
MAC register clear
LDC
Load to control register
LDS
Load to system register
NOP
No operation
RTE
Return from exception handling
SETT
T bit set
SLEEP
Shift into power-down mode
STC
Store control register data
STS
Store system register data
TRAPA
Trap exception handling
Total
56
Number of
Instructions
14
14
7
31
133
Rev. 7.00 Jan 31, 2006 page 32 of 658
REJ09B0272-0700