SH7032 Datasheet, PDF (213/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 9 Direct Memory Access Controller (DMAC)
Bit 11: Bit 10: Bit 9: Bit 8:
RS3 RS2 RS1 RS0 Description
0
0
0
0
DREQ (External request*¹, dual address mode) (Initial value)
0
0
0
1
Reserved (illegal setting)
0
0
1
0
DREQ (External request*¹, single address mode*²)
0
0
1
1
DREQ (External request*¹, single address mode*³)
0
1
0
0
RXI0 (On-chip serial communication interface 0 receive data
full interrupt transfer request)*⁴
0
1
0
1
TXI0 (On-chip serial communication interface 0 transmit data
empty interrupt transfer request)*⁴
0
1
1
0
RXI1 (On-chip serial communication interface 1 receive data
full interrupt transfer request)*⁴
0
1
1
1
TXI1 (On-chip serial communication interface 1 transmit data
empty interrupt transfer request)*⁴
1
0
0
0
IMIA0 (On-chip ITU0 input capture/compare match A interrupt
transfer request)*⁴
1
0
0
1
IMIA1 (On-chip ITU1 input capture/compare match A interrupt
transfer request)*⁴
1
0
1
0
IMIA2 (On-chip ITU2 input capture/compare match A interrupt
transfer request)*⁴
1
0
1
1
IMIA3 (On-chip ITU3 input capture/compare match A interrupt
transfer request)*⁴
1
1
0
0
Auto-request (Transfer requests automatically generated
within DMAC)*⁴
1
1
0
1
ADI (A/D conversion end interrupt request of on-chip A/D
converter)*⁴
1
1
1
0
Reserved (illegal setting)
1
1
1
1
Reserved (illegal setting)
SCI0, SCI1: Serial communication interface channels 0 and 1
ITU0–ITU3: Channels 0–3 of the 16-bit integrated timer pulse unit
Notes: 1. These bits are valid only in channels 0 and 1. None of these request sources can be
selected in channels 2 and 3.
2. Transfer from memory-mapped external device or external memory to external device
with DACK.
3. Transfer from external device with DACK to memory-mapped external device or
external memory.
4. Dual address mode.
Rev. 7.00 Jan 31, 2006 page 187 of 658
REJ09B0272-0700