SH7032 Datasheet, PDF (207/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 9 Direct Memory Access Controller (DMAC)
9.1.2 Block Diagram
Figure 9.1 shows a block diagram of the DMAC.
On-chip
ROM
On-chip
RAM
On-chip
supporting
module
DREQ0, DREQ1
ITU
SCI
A/D converter
DACK0, DACK1
DEIn
External
ROM
External
RAM
External device
(memory-
mapped)
External
device (with
acknowledge)
Iteration
control
Register
control
Start-up
control
Request
priority
control
Bus interface
Bus controller
SARn
DARn
TCRn
CHCRn
DMAOR
DMAC
DMAOR: DMA operation register
SARn: DMA source address register
DARn: DMA destination address register
TCRn: DMA transfer count register
CHCRn: DMA channel control register
DEIn: DMA transfer-end interrupt request to CPU
n: 0-3
Figure 9.1 Block Diagram of DMAC
Rev. 7.00 Jan 31, 2006 page 181 of 658
REJ09B0272-0700