SH7032 Datasheet, PDF (326/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
10.6.7 Contention Between Counter Clearing by Input Capture and Counter Increment
If an input capture signal and counter increment signal occur simultaneously, the counter is
cleared by the input capture signal. The counter is not incremented by the increment signal. The
TCNT value before the counter is cleared is transferred to the general register. The timing is
shown in figure 10.64.
CK
Input capture
signal
Counter
clear signal
TCNT
input clock
TCNT
N
H'0000
GR
N
Figure 10.64 Contention between Counter Clearing by Input Capture and Counter
Increment
Rev. 7.00 Jan 31, 2006 page 300 of 658
REJ09B0272-0700