SH7032 Datasheet, PDF (115/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 6 User Break Controller (UBC)
Bits 5 and 4—Instruction Fetch/Data Access Select (ID1, ID0): ID1 and ID0 select whether to
break on instruction fetch and/or data access bus cycles.
Bit 5: ID1
0
1
Bit 4: ID0
0
1
0
1
Description
No break interrupt occurs
Break only on instruction fetch cycles
Break only on data access cycles
Break on both instruction fetch and data access cycles
(Initial value)
Bits 3 and 2—Read/Write Select (RW1, RW0): RW1 and RW0 select whether to break on read
and/or write access cycles.
Bit 3: RW1 Bit 2: RW0 Description
0
0
No break interrupt occurs
1
Break only on read cycles
1
0
Break only on write cycles
1
Break on both read and write cycles
(Initial value)
Bits 1 and 0 —Operand Size Select (SZ1, SZ0): SZ1 and SZ0 select the bus cycle operand size
as a break condition.
Bit 1: SZ1 Bit 0: SZ0 Description
0
0
Operand size is not a break condition
(Initial value)
1
Break on byte access
1
0
Break on word access
1
Break on longword access
Note:
When setting a break on an instruction fetch, clear the SZ0 bit to 0. All instructions will be
considered to be accessed as words (even those instructions in on-chip memory for which
two instructions can be fetched simultaneously in a single bus cycle). Instruction fetch is by
word access and CPU/DMAC data access is by the specified operand size. The access is
not determined by the bus width of the space being accessed.
Rev. 7.00 Jan 31, 2006 page 89 of 658
REJ09B0272-0700