SH7032 Datasheet, PDF (530/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 20 Electrical Characteristics
CK
A21–A0
RAS
CAS
RD(Read)
WRH, WRL,
WR(Read)
DACK0
DACK1
(Read)
AD15–AD0
DPH, DPL
(Read)
RD(Write)
WRH, WRL,
WR(Write)
AD15–AD0
(Write)
DPH, DPL
(Write)
DACK0
DACK1
(Write)
T_p
T_r
T_c
t_AD
t_AD
Row
t_RASD1
t_RAH
Column
t_RASD2
t_RDD
t_DS
t_ASC
t_CASD1
t_RSD
t_WCH
t_DACD1 t_DACD2
t_ACC1^{*2 tCAC1*1}
t_RAC1^*3
t_RDS
t_RDH^*4
t_WSD3
t_WCS
t_WDD2
t_WSD4
t_WDH
t_WPDD2
t_WPDH
t_DACD4 t_DACD5
Notes: 1. For t_CAC1, use t_cyc × 0.65 – 35 (for 35% duty) or t_cyc × 0.5 – 35 (for 50% duty) instead
of t_cyc – t_AD – t_ASC – t_RDS.
2. For t_ACC1, use t_cyc – 44 instead of t_cyc – t_AD – t_RDS.
3. For t_RAC1, use t_cyc × 1.5 – 35 instead of t_cyc × 1.5 – t_RASD1 – t_RDS.
4. t_RDH is measured from A21–A0, RAS, or CAS, whichever is negated first.
Figure 20.24 DRAM Bus Cycle (Short-Pitch, Normal Mode)
Rev. 7.00 Jan 31, 2006 page 504 of 658
REJ09B0272-0700