SH7032 Datasheet, PDF (72/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 2 CPU
From any state when
RES = 0 and NMI = 1
From any state when
RES = 0 and NMI = 0
Power-on reset state
RES = 0, NMI = 0
RES = 0, NMI = 1
Manual reset state
When an interrupt source
or DMA address error occurs
RES = 1,
NMI = 1
RES = 1,
NMI = 0
Exception handling state
Reset states
Bus request
cleared
Bus request
generated
Bus-release-state
Exception
handling
source occurs
NMI interrupt
source occurs
Exception
handling
ends
Bus request
generated
Bus request
cleared
Bus request
generated
Bus request
cleared
Program execution state
SLEEP instruction
with SBY bit cleared
SLEEP
instruction with
SBY bit set
Sleep mode
Standby mode
Power-down state
Figure 2.6 Transitions Between Processing States
Rev. 7.00 Jan 31, 2006 page 46 of 658
REJ09B0272-0700