SH7032 Datasheet, PDF (673/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix A On-Chip Supporting Module Registers
A.3 Register Status in Reset and Power-Down States
Table A.77 Register Status in Reset and Power-Down States
Reset State
Category
Abbreviation Power On Manual
CPU
R0–R15
Initialized Initialized
SR
GBR
VBR
MACH,MACL
PR
PC
Interrupt controller (INTC) IPRA–IPRE
Initialized Initialized
ICR
User break controller (UBC) BARH,BARL
Initialized Initialized
BAMRH,BAMRL
BBR
Bus state controller (BSC) BCR
Initialized Held
WCR1–WCR3
DCR
RCR
RTSCR
RTCNT
RTCOR
PCR
Direct memory access
controller (DMAC)
SAR0–SAR3
DAR0–DAR3
Initialized Initialized
TCR0–TCR3
CHCR0–
CHCR3
DMAOR
Power-Down State
Standby Sleep
Held
Held
Held
Held
Held
Held
Held
Held
Initialized Held
Rev. 7.00 Jan 31, 2006 page 647 of 658
REJ09B0272-0700