SH7032 Datasheet, PDF (495/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 19 Power-Down State
19.4.2 Exiting Standby Mode
Standby mode is exited by an NMI interrupt, a power-on reset, or a manual reset.
Exit by NMI: When a rising edge or falling edge (as selected by the NMIE bit in the interrupt
control register (ICR) of the interrupt controller (INTC)) is detected at the NMI pin, the clock
oscillator begins operating. At first, clock pulses are supplied only to the watchdog timer. After the
time that was selected before entering standby mode using clock select bits 2–0 (CKS2–CKS0) in
the timer control/status register (TCSR) of the watchdog timer (WDT), the watchdog timer
overflows. After the overflow, the clock is considered stable and supplied to the entire chip.
Standby mode is exited and the NMI exception handling sequence begins.
When standby mode is cleared by an NMI interrupt, bits CKS2–CKS0 must be set so that the
WDT overflow interval is equal to or greater than the clock settling time. When standby mode is
cleared when the falling edge has been selected with the NMI bit, be sure that the NMI pin is high
when standby mode is entered (when the clock is halted) and low when the chip returns from
standby mode (clock starts up after the oscillator is stabilized). Likewise, when standby mode is
cleared when the rising edge has been selected with the NMI bit, be sure that the NMI pin is low
when standby mode is entered (clock halted) and high when the chip returns from standby mode
(clock starts up after the oscillator is stabilized).
Exit by Power-On Reset: If the RES signal goes low while the NMI signal is high, standby mode
is exited and the power-on reset state is entered. If the NMI signal is brought from low to high in
order to set the chip for a power-on reset, standby mode will not be exited by an NMI interrupt,
because the NMI signal is initialized for the falling edge in standby mode (by the NMIE bit).
Exit by Manual Reset: If the RES signal goes low while the NMI signal is low, standby mode is
exited and the manual reset state is entered. If the NMI signal is brought from high to low in order
to set the chip for a manual reset, standby mode will first be exited by an NMI interrupt, because
the NMI signal is initialized for the falling edge in standby mode (by the NMIE bit).
19.4.3 Standby Mode Application
In this example, standby mode is entered on the falling edge of the NMI signal and exited on the
rising edge of the NMI signal. Figure 19.1 shows the timing.
After an NMI interrupt is accepted on a high-to-low transition at the NMI pin while NMI edge
select bit NMIE in the interrupt control register (ICR) is cleared to 0 to select falling edge
detection, the NMI exception handling routine sets NMIE to 1 (selecting rising edge detection)
and sets the SBY bit to 1. Finally, it executes a SLEEP instruction to enter standby mode.
Standby mode is exited on the rising edge of the NMI signal.
Rev. 7.00 Jan 31, 2006 page 469 of 658
REJ09B0272-0700