SH7032 Datasheet, PDF (611/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix A On-Chip Supporting Module Registers
A.2.17 Timer Status Registers 0–4 (TSR0–TSR4)
ITU
Start Address: H'5FFFF07 (channel 0), H'5FFFF11 (channel 1), H'5FFFF1B (channel 2),
H'5FFFF25 (channel 3), H'5FFFF35 (channel 4),
Bus Width: 8
Bit
7
6
5
4
Initial value
—
—
—
—
*¹
1
1
1
Read/Write
—
—
—
—
Notes: 1. Undetermined
2. Only 0 can be written, to clear the flag.
3
2
1
0
—
OVF IMFB IMFA
1
0
0
0
— R/(W)*² R/(W)*² R/(W)*²
Table A.18 TSR0–TSR4 Bit Functions
Bit Bit name
2 Overflow flag (OVF)
1 Input capture/compare match
flag B (IMFB)
0 Input capture/compare match
flag A (IMFA)
Value
0
1
0
1
0
1
Description
Clear conditions: 0 is written in OVF after
reading OVF = 1
(Initial value)
Set conditions: TCNT value overflows (H'FFFF
→ H'0000) or underflows (H'FFFF → H'0000)
Clear conditions: 0 is written in IMFB after
reading IMFB = 1
(Initial value)
Set conditions: (1) When GRB is functioning as
the output compare register, and TCNT = GRB;
(2) When GRB is functioning as the input
capture register, and the TCNT value is
transferred to GRB by the input capture signal
Clear conditions: 0 is written in IMFA after
reading IMFA = 1
(Initial value)
Set conditions: (1) When GRA is functioning as
the output compare register, and TCNT = GRA;
(2) When GRA is functioning as the input
capture register, and the TCNT value is
transferred to GRA by the input capture signal
Rev. 7.00 Jan 31, 2006 page 585 of 658
REJ09B0272-0700