SH7032 Datasheet, PDF (346/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 11 Programmable Timing Pattern Controller (TPC)
Bits 3–0—Next Data 3–0 (NDR3–NDR0): NDR3–NDR0 store the next output data for TPC
output group 0.
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
—
—
—
—
NDR3 NDR2 NDR1 NDR0
1
1
1
1
0
0
0
0
—
—
—
—
R/W R/W R/W R/W
11.2.4 Next Data Register B (NDRB)
NDRB is an eight-bit read/write register that stores the next output data for TPC output groups 3
and 2 (TP15–TP8). When used for TPC output, the contents of NDRB are transferred to the
corresponding PBDR bits when the ITU compare match specified in the TPC output control
register, TPCR, occurs.
The address of NDRB differs depending on whether TPCR settings select the same trigger or
different triggers for TPC output groups 3 and 2. NDRB is initialized to H'00 by a reset. It is not
initialized in standby mode.
Same Trigger for TPC Output Groups 3 and 2: If TPC output groups 3 and 2 are triggered by
the same compare match, the address of NDRB is H'FFFFF4. The upper 4 bits become group 3
and the lower 4 bits become group 2. Address H'5FFFFF6 consists entirely of reserved bits. These
bits are always read as 1, and the write value should always be 1.
Address H'5FFFFF4
Bits 7–4—Next Data 15–12 (NDR15–NDR12): NDR15–NDR12 store the next output data for
TPC output group 3.
Bits 3–0—Next Data 11–8 (NDR11–NDR8): NDR11–NDR8 store the next output data for TPC
output group 2.
Bit
Initial value
Read/Write
7
NDR15
0
R/W
6
NDR14
0
R/W
5
NDR13
0
R/W
4
NDR12
0
R/W
3
NDR11
0
R/W
2
NDR10
0
R/W
1
NDR9
0
R/W
0
NDR8
0
R/W
Rev. 7.00 Jan 31, 2006 page 320 of 658
REJ09B0272-0700