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SH7032 Datasheet, PDF (557/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer
Section 20 Electrical Characteristics
(3) Bus Timing
Tables 20.20 show the bus timing.
Table 20.20 Bus Timing (1)
Conditions: VCC = 3.3 V ±0.3V, AVCC = 3.3 V ±0.3V, AVCC = VCC ±0.3V, AVref = 3.0 V to
AVCC, VSS = AVSS = 0 V, φ = 20 MHz*1, Ta = –20 to +75°C*2
Notes: 1. ROMless products
2. Regular-specification products; for wide-temperature-range products, Ta = –40 to
+85°C
Item
Symbol Min
Max Unit Figures
Address delay time
tAD
—
20*1 ns
20.52, 20.53, 20.55–
20.58, 20.63, 20.64
CS delay time 1
tCSD1
CS delay time 2
tCSD2
CS delay time 3
tCSD3
CS delay time 4
tCSD4
Access time 1*6 35% duty*2 tRDAC1
from read strobe 50% duty
Access time 2*6 35% duty*2 tRDAC2
from read strobe 50% duty
Access time 3*6 35% duty*2 tRDAC3
from read strobe 50% duty
Read strobe delay time
tRSD
—
25
—
25
—
25
—
25
tcyc × 0.65 – 20
—
tcyc × 0.5 – 20
—
tcyc × (n+1.65) – 20*3 —
tcyc × (n+1.5)– 20*3 —
tcyc × (n+0.65) – 20*3 —
tcyc × (n+0.5)– 20*3 —
—
20
ns 20.52, 20.53, 20.64
ns
ns 20.63
ns
ns 20.52
ns
ns 20.53, 20.54
ns
ns 20.63
ns
ns 20.52, 20.53, 20.55–
20.59, 20.63
Read data setup time
tRDS
15
— ns 20.52, 20.53, 20.55–
20.58, 20.63
Read data hold time
tRDH
0
Write strobe delay time 1 tWSD1 —
— ns
20 ns 20.53, 20.57, 20.58,
20.63, 20.64
Write strobe delay time 2 tWSD2 —
20 ns 20.53, 20.57, 20.58,
20.63
Write strobe delay time 3 tWSD3 —
Write strobe delay time 4 tWSD4 —
20 ns 20.55, 20.56
20 ns 20.55, 20.56, 20.64
Rev. 7.00 Jan 31, 2006 page 531 of 658
REJ09B0272-0700