SH7032 Datasheet, PDF (103/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 5 Interrupt Controller (INTC)
9. The CPU accesses the exception vector table at the entry for the vector number of the
accepted interrupt, reads the start address of the exception handling routine, branches to that
address, and starts executing the program there. This branch is not delayed.
Note: * A request for an external interrupt (IRQ) designated as edge-detected is held pending once
only. An external interrupt designated as level-detected is held pending as long as the
interrupt request continues, but if the request is cleared before the CPU next accepts an
interrupt, the interrupt request is regarded as not having been made.
Interrupt requests from on-chip supporting modules are level requests. When the status
flag in a particular module is set, an interrupt is requested. For details, see the descriptions
of the individual modules. Note that the interrupt request will be continued unless an
operation described in "Clearing Conditions" is performed.
Rev. 7.00 Jan 31, 2006 page 77 of 658
REJ09B0272-0700