SH7032 Datasheet, PDF (197/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 8 Bus State Controller (BSC)
If BACK has not gone low after waiting for the maximum
number of states* before the SuperH releases the bus, return
BREQ to the high level.
BREQ
BACK
Refresh request
BACK does not go low.
Note: * For details see section 8.11.3, Maximum Number of States from BREQ Input to Bus Release.
Figure 8.37 BACK Operation in Response to Refresh Request (2)
3. If a refresh request is generated during DMA transfer in burst mode, the DMA transfer is
halted and a refresh is executed.
8.10.2 BACK Operation
1. BACK operation
When an internal refresh is requested during an attempt to assert the BACK signal and BACK
is not asserted but remains high, a momentary narrow pulse-shaped spike may be output, as
shown below.
BREQ
BACK
Refresh demand
Spike pulse width is approx. 2 to 5 ns.
2. Preventing spikes in the BACK signal
The following measures should be taken to prevent spikes in the BACK signal:
a. When BREQ is input to release the bus, make sure that a conflict with a refresh operation
does not occur. Stop the refresh operation or operate the refresh timer counter (RTCNT) or
the refresh time constant register (RTCOR) of the bus controller (BSC) to shift the refresh
timing.
b. A spike in the BACK signal has a narrow pulse width of approximately 2 to 5 ns, which
can be eliminated by using a capacitor as shown in the figure below.
Rev. 7.00 Jan 31, 2006 page 171 of 658
REJ09B0272-0700