SH7032 Datasheet, PDF (130/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 8 Bus State Controller (BSC)
• Refresh counter can be used as an interval timer
 Interrupt request generated at compare match (CMI interrupt request signal)
8.1.2 Block Diagram
Figure 8.1 shows a block diagram of the bus state controller.
WAIT
RD
WRH, WRL
HBS, LBS
AH
CS7 to CS0
Wait control
unit
Area control
unit
CASH, CASL
RAS
CMI interrupt request
DRAM
control
unit
Bus
interface
WCR1
WCR2
WCR3
BCR
DCR
RCR
RTCSR
RTCNT
DPH, DPL
PEI interrupt request
Parity control
unit
Comparator
RTCOR
Interrupt
controller
WCR: Wait state control register
BCR: Bus control register
DCR: DRAM area control register
RCR: Refresh control register
PCR
BSC
RTCSR: Refresh timer control/status register
RTCNT: Refresh timer counter
RTCOR: Refresh time constant register
PCR: Parity control register
Figure 8.1 Block Diagram of BSC
Rev. 7.00 Jan 31, 2006 page 104 of 658
REJ09B0272-0700