SH7032 Datasheet, PDF (675/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix A On-Chip Supporting Module Registers
Reset State
Power-Down State
Category
Abbreviation Power On Manual
Standby Sleep
A/D converter
ADDRA–
ADDRD
Initialized Initialized Initialized Held
ADCSR
ADCR
Pin function controller
(PFC)
PAIOR,PBIOR
PACR1,PACR2,
PBCR1,PBCR2
Initialized
Held
Held
Held
CASCR
Parallel I/O ports (I/O)
PADR,PBDR
PCDR
Initialized
*³
Held
*³
Held
*³
Held
*³
Power-down-state related SBYCR
Initialized Initialized Held
Held
Notes: 1. Bits 7–5 (OVF, WT/IT, TME) are initialized, bits 2–0 (CKS2–CKS0) are held.
2. Not initialized in the case of a reset by the WDT.
3. Bits 15–8 are always undetermined, bits 7–0 always reflect the state of the
corresponding pin.
Rev. 7.00 Jan 31, 2006 page 649 of 658
REJ09B0272-0700