SH7032 Datasheet, PDF (411/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Serial Communication Interface (SCI)
1
Serial
data
Start
bit
0 D₀
Parity Stop Start
Data bit bit bit
D₁
D₇ 0/1 1 0 D₀
Parity Stop
Data bit bit
1
D₁
D₇ 0/1
1 ^{Idle (mark)}
state
TDRE
TEND
TXI TXI interrupt
request handler writes
data in TDR
and clears
TDRE to 0
TXI
request
TEI request
1 frame
Figure 13.6 Example of SCI Transmit Operation in Asynchronous Mode (8-Bit Data with
Parity and One Stop Bit)
Receiving Serial Data (Asynchronous Mode): Figure 13.7 shows a sample flowchart for
receiving serial data. The procedure for receiving serial data is listed below.
1. SCI initialization: select the RxD pin function with the PFC.
2. Receive error handling and break detection: if a receive error occurs, read the ORER, PER and
FER bits in SSR to identify the error. After executing the necessary error handling, clear
ORER, PER, and FER all to 0. Receiving cannot resume if ORER, PER, or FER remains set to
1. When a framing error occurs, the RxD pin can be read to detect the break state.
3. SCI status check and receive data read: read the serial status register (SR), check that RDRF is
set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0. The
RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1.
4. To continue receiving serial data: read RDRF and RDR, and clear RDRF to 0 before the stop
bit of the current frame is received. If the DMAC is started by a receive-data-full interrupt
(RXI) to read RDR, the RDRF bit is cleared automatically, so this step is unnecessary.
Rev. 7.00 Jan 31, 2006 page 385 of 658
REJ09B0272-0700