SH7032 Datasheet, PDF (642/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix A On-Chip Supporting Module Registers
Table A.45 DCR Bit Functions
Bit Bit Name
Value Description
15 2-CAS system/2-WE
system (CW2)
0
2-CAS system: CASH, CASL, and WRL signals are
valid
(Initial value)
1
2-WE system: CASL, WRH, and WRL signals are
valid
14 RAS down (RASD)
0
RAS up mode: Returns RAS signal to high and
waits for next DRAM access
(Initial value)
1
RAS down mode: Leaves RAS signal low and waits
for next DRAM access
13 Number of RAS pre-charge 0
cycles (TPC)
1
1-cycle pre-charge cycle inserted
2-cycle pre-charge cycle inserted
(Initial value)
12 Burst operation enable (BE) 0
Normal mode: Full access
(Initial value)
1
High-speed page mode: Burst operation
11 CAS duty (CDTY)
0
CAS signal high width duty ratio is 50% (Initial value)
1
CAS signal high width duty ratio is 35%
10 Multiplex enable (MXE)
0
Row address and column address not multiplexed
(Initial value)
1
Row address and column address multiplexed
9,8 Multiplex shift count 1,0
(MXC1, MXC0)
Row address shift
(MXE = 1)
Row address for comparison
during burst (MXE = 0 or 1)
0 0 8 bits (Initial value) A27–A8
(Initial value)
0 1 9 bits
A27–A9
1 0 10 bits
A27–A10
1 1 Reserved
Reserved
Rev. 7.00 Jan 31, 2006 page 616 of 658
REJ09B0272-0700