SH7032 Datasheet, PDF (43/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 2 CPU
Section 2 CPU
2.1 Register Configuration
The register set consists of sixteen 32-bit general registers, three 32-bit control registers, and four
32-bit system registers.
2.1.1 General Registers (Rn)
General registers Rn consist of sixteen 32-bit registers (R0–R15). General registers are used for
data processing and address calculation. Register R0 also functions as an index register. For some
instructions, the R0 register must be used. Register R15 functions as a stack pointer to save or
restore status registers (SR) and the program counter (PC) during exception handling.
31
R0
R1
R2
R3
R4
0
R0 functions as an index register
in the indexed register addressing
mode and indirect indexed GBR
addressing mode. In some instruc-
tions, R0 functions as a source
register or a destination register.
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15, SP (hardware stack pointer) R15 functions as a stack pointer (SP)
during exception handling.
Figure 2.1 General Registers (Rn)
Rev. 7.00 Jan 31, 2006 page 17 of 658
REJ09B0272-0700