SH7032 Datasheet, PDF (270/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
10.2.8 Buffer Registers A and B (BRA, BRB)
Each buffer register is a 16-bit read/write register that is used in buffer mode. The ITU has four
buffer registers, two each for channels 3 and 4. Buffer operation can be set independently by the
timer function control register (TFCR) bits BFB4, BFA4, BFB3, and BFB3. The buffer registers
are paired with the general registers and their function changes automatically to match the function
of corresponding general register.
The buffer registers are connected to the CPU by a 16-bit bus, so they can be written or read by
either word or byte access. Buffer registers are initialized to H'FFFF by a reset and in standby
mode.
Table 10.6 Buffer Registers A and B (BRA, BRB)
Channel
3
4
Abbreviation
BRA3, BRB3
BRA4, BRB4
Function
When used for buffer operation:
When the corresponding GRA and GRB are output compare
registers, the buffer registers function as output compare buffer
registers that can automatically transfer the BRA and BRB values to
GRA and GRB upon a compare match.
When the corresponding GRA and GRB are input capture registers,
the buffer registers function as input capture buffer registers that can
automatically transfer the values stored until an input capture in the
GRA and GRB to the BRA and BRB.
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
15
14
13
12
11
10
9
8
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 7.00 Jan 31, 2006 page 244 of 658
REJ09B0272-0700