SH7032 Datasheet, PDF (55/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Instruction Format
nm format
Source Operand
mmmm: Register
direct
Destination
Operand
nnnn: Register
direct
Section 2 CPU
Example
ADD Rm,Rn
15
0
xxxx nnnn mmmm xxxx
md format
15
0
xxxx xxxx mmmm dddd
nd4 format
15
0
xxxx xxxx nnnn dddd
nmd format
15
0
xxxx nnnn mmmm dddd
mmmm: Register
direct
nnnn: Register
indirect
mmmm: Register
MACH, MACL
indirect with post-
increment (multiply-
and-accumulate)
nnnn: Register
indirect with post-
increment (multiply-
and-accumulate)*
mmmm: Register
indirect with
post-increment
nnnn: Register
direct
mmmm: Register
direct
nnnn: Register
indirect with
pre-decrement
mmmm: Register
direct
nnnn: Indexed
register indirect
MOV.L Rm,@Rn
MAC.W
@Rm+,@Rn+
MOV.L @Rm+,Rn
MOV.L Rm,@-Rn
MOV.L
Rm,@(R0,Rn)
mmmmdddd:
Register indirect
with displacement
R0 (Register
direct)
MOV.B
@(disp,Rn),R0
R0 (Register direct) nnnndddd:
MOV.B
Register indirect _{R0,@(disp,Rn)}
with displacement
mmmm: Register
direct
nnnndddd:
MOV.L
Register indirect _{Rm,@(disp,Rn)}
with displacement
mmmmdddd:
Register indirect
with displacement
nnnn: Register
direct
MOV.L
@(disp,Rm),Rn
Rev. 7.00 Jan 31, 2006 page 29 of 658
REJ09B0272-0700