SH7032 Datasheet, PDF (285/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

TCNT value
H'FFFF
H'0000
Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
Time
STR0–STR4
OVF
Figure 10.15 Free-Running Counter Operation
TCNT value
GR
H'0000
Counter cleared by
GR compare match
Time
STR0–STR4
IMF
Figure 10.16 Periodic Counter Operation
• TCNT counter timing
Internal clock source: Bits TPSC2–TPSC0 in TCR select the system clock (CK) or one of three
internal clock sources (φ/2, φ/4, φ/8) obtained by prescaling the system clock. Figure 10.17
shows the timing.
External clock source: The external clock input pin (TCLKA–TCLKD) source is selected by
bits TPSC2–TPSC0 in TCR and its valid edges are selected with the CKEG1 and CKEG0 bits
in TCR. The rising edge, falling edge, or both edges can be selected. The pulse width of the
external clock signal must be at least 1.5 system clocks when a single edge is selected and at
least 2.5 system clocks when both edges are selected. Shorter pulses will not be counted
correctly. Figure 10.18 shows the timing when both edges are detected.
Rev. 7.00 Jan 31, 2006 page 259 of 658
REJ09B0272-0700