SH7032 Datasheet, PDF (166/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 8 Bus State Controller (BSC)
T1
T2
CK
A21–A0
CSn
RD
Read
AD15–AD0
When
RDDTY = 0
When
RDDTY = 1
WRH, WRL
Write
AD15–AD0
Figure 8.12 Basic Timing of External Memory Space Access (2-State Read Timing)
High-level duties of 35% and 50% can be selected for the RD signal using the RD duty bit
(RDDTY) in BCR. When RDDTY is set to 1, the high-level duty is 35% of the T1 state, enabling
longer access times for external devices. Only set to 1 when the operating frequency is a minimum
of 10 MHz.
Rev. 7.00 Jan 31, 2006 page 140 of 658
REJ09B0272-0700