SH7032 Datasheet, PDF (34/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 1 Overview
1.2 Block Diagram
RES
WDTOVF
MD2
MD1
MD0
NMI
CK
EXTAL
XTAL
V_CC(V_PP)^*2
V_CC
V_CC
V_CC
V_CC
V_CC
V_CC
V_CC
V_SS
V_SS
V_SS
V_SS
V_SS
V_SS
V_SS
V_SS
V_SS
V_SS
AV_ref
AV_CC
AV_SS
Port A
Address
PROM or
masked ROM^*1
RAM^*1
CPU
Direct
memory
access
controller
Interrupt ^User
controller
break
controller
Bus state controller
Serial communi-
cation interface
(2 channels)
Programmable
timing pattern
controller
16-bit
integrated timer
pulse unit
A/D _Watchdog
converter _timer
Port C
Port B
: Peripheral address bus (24 bits)
: Peripheral data bus (16 bits)
: Internal address bus (24 bits)
: Internal upper data bus (16 bits)
: Internal lower data bus (16 bits)
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0 (HBS)
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Notes: 1. The SH7032 has 8 kB of RAM and no PROM or masked ROM. The SH7034 has 4 kB
of RAM and 64 kB of PROM or masked ROM.
2. VPP: SH7034 (PROM version)
Figure 1.1 Block Diagram
Rev. 7.00 Jan 31, 2006 page 8 of 658
REJ09B0272-0700