SH7032 Datasheet, PDF (211/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 9 Direct Memory Access Controller (DMAC)
9.2.3 DMA Transfer Count Registers 0–3 (TCR0–TCR3)
DMA transfer count registers 0–3 (TCR0–TCR3) are 16-bit read/write registers that specify the
DMA transfer count (bytes or words). The number of transfers is 1 when the setting is H'0001,
65535 when the setting is H'FFFF, and 65536 (the maximum) when H'0000 is set. During a DMA
transfer, these registers indicate the remaining transfer count. The initial value after a reset or in
standby mode is undefined.
Bit
15
14
13
12
11
10
9
8
Initial value
Read/Write
—
—
—
—
—
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
—
—
—
—
—
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
9.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3)
DMA channel control registers 0–3 (CHCR0–CHCR3) are 16-bit read/write registers that control
the DMA transfer mode. They also indicate the DMA transfer status. They are initialized to
H'0000 by a reset and in standby mode.
Bit
Initial value
Read/Write
15
14
13
12
11
10
9
8
DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
7
6
5
4
3
2
1
0
AM
AL
DS
TM
TS
IE
TE
DE
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/(W)*² R/(W)*² R/(W)*² R/W
R/W
R/W R/(W)*¹ R/W
Notes: 1. Only 0 can be written, to clear the flag.
2. Writing is valid only for CHCR0 and CHCR1.
Rev. 7.00 Jan 31, 2006 page 185 of 658
REJ09B0272-0700