SH7032 Datasheet, PDF (389/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Serial Communication Interface (SCI)
(SMR) before setting CKE1 and CKE0. For further details on selection of the SCI clock source,
see table 13.9 in section 13.3, Operation.
Bit 1: Bit 0:
CKE1 CKE0 Description*¹
0
0
Asynchronous mode Internal clock, SCK pin used for input pin (input signal
is ignored) or output pin (output level is undefined)*²
(Initial value)
Synchronous mode
Internal clock, SCK pin used for serial clock output*²
(Initial value)
0
1
Asynchronous mode Internal clock, SCK pin used for clock output*³
Synchronous mode
Internal clock, SCK pin used for serial clock output
1
0
Asynchronous mode External clock, SCK pin used for clock input*⁴
Synchronous mode
External clock, SCK pin used for serial clock input
1
1
Asynchronous mode External clock, SCK pin used for clock input*⁴
Synchronous mode
External clock, SCK pin used for serial clock input
Notes: 1. The SCK pin is multiplexed with other functions. Set the pin function controller (PFC) to
select the SCK function and SCK input/output for the SCK pin.
2. Initial value
3. The output clock frequency is the same as the bit rate.
4. The input clock frequency is 16 times the bit rate.
13.2.7 Serial Status Register
The serial status register (SSR) is an 8-bit register containing multiprocessor bit values, and status
flags that indicate the SCI operating status.
The CPU can always read and write to SSR, but cannot write 1 in the status flags (TDRE, RDRF,
ORER, PER, and FER). These flags can be cleared to 0 only if they have first been read (after
being set to 1). Bits 2 (TEND) and 1 (MPB) are read-only bits that cannot be written. SSR is
initialized to H'84 by a reset and in standby mode.
Bit
7
6
5
TDRE RDRF ORER
Initial value
1
0
0
Read/Write
R/(W)* R/(W)* R/(W)*
Note: * Only 0 can be written, to clear the flag.
4
FER
0
R/(W)*
3
PER
0
R/(W)*
2
TEND
1
R
1
MPB
0
R
0
MPBT
0
R/W
Rev. 7.00 Jan 31, 2006 page 363 of 658
REJ09B0272-0700