SH7032 Datasheet, PDF (494/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 19 Power-Down State
19.4 Standby Mode
19.4.1 Transition to Standby Mode
To enter standby mode, set the standby bit (SBY) to 1 in the standby control register (SBYCR),
then execute the SLEEP instruction. The chip switches from the program execution state to
standby mode. Standby mode greatly reduces power consumption by halting not only the CPU,
but the clock and on-chip supporting modules as well. Some registers of the on-chip supporting
modules are initialized, others are not (See table 19.3). As long as the specified voltage is
supplied, however, CPU register contents and on-chip RAM data are held. The I/O port state (hold
or high impedance) depends on the port high-impedance bit (HIZ) in SBYCR. For details on the
states of these pins, see appendix B, Pin States.
Table 19.3 Register States in Standby Mode
Module
Interrupt controller (INTC)
User break controller (UBC)
Bus state controller (BSC)
Pin function controller (PFC)
I/O ports
Direct memory access
controller (DMAC)
Watchdog timer (WDT)
16-bit integrated timer pulse
unit (ITU)
Programmable timing pattern
controller (TPC)
Serial communication interface
(SCI)
A/D converter (A/D)
Power-down state register
Registers Initialized
—
—
—
—
—
All registers
• Bits 7–5 (OVF, WT/IT, TME)
in timer control status
register (TCSR)
• Reset control/status register
(RSTCSR)
All registers
—
• Receive data register (RDR)
• Transmit data register (TDR)
• Serial mode register (SMR)
• Serial control register (SCR)
• Serial status register (SSR)
• Bit rate register (BBR)
All registers
—
Registers That Hold Data
All registers
All registers
All registers
All registers
All registers
—
• Bits 2–0 (CKS2–CKS0) in
timer control status
register (TCSR)
• Timer counter (TCNT)
—
All registers
—
—
Standby control register
(SBYCR)
Rev. 7.00 Jan 31, 2006 page 468 of 658
REJ09B0272-0700