SH7032 Datasheet, PDF (70/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 2 CPU
Instruction Code
MSB
LSB
1100 00M
D
imm/disp
1100 01M
disp
D
1100 10M
imm
D
1100 11M
imm
D
1101 Rn
1110 Rn
1111
disp
imm
...
Fx: 0000
MD: 00
Fx: 0001
MD: 01
Fx: 0010
MD: 10
Fx: 0011–1111
MD: 11
MOV.B R0,@ MOV.W R0,@ MOV.L R0,@ TRAPA #imm:8
(disp:8,GBR) (disp:8,GBR) (disp:8,GBR)
MOV.B
@(disp:8,
GBR),R0
MOV.W
@(disp:8,
GBR),R0
MOV.L
@(disp:8,
GBR),R0
MOVA
@(disp:8,
PC),R0
TST
#imm:8,R0
AND
#imm:8,R0
XOR
#imm:8,R0
OR
#imm:8,R0
TST.B
#imm:8,
@(R0,GBR)
AND.B
#imm:8,
@(R0,GBR)
XOR.B
#imm:8,
@(R0,GBR)
OR.B
#imm:8,
@(R0,GBR)
MOV.L @(disp:8,PC),Rn
MOV #imm:8,Rn
Rev. 7.00 Jan 31, 2006 page 44 of 658
REJ09B0272-0700