SH7032 Datasheet, PDF (247/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 9 Direct Memory Access Controller (DMAC)
6. Notes on use of the SLEEP instruction
a. Operation contents
When a DMAC bus cycle is entered immediately after executing a SLEEP instruction,
there are cases when DMA transfer is not carried out correctly.
b. Remedy
• Stop operation (for example, by clearing the DMA enable bit (DE) in the DMA channel
control register (CHCRn)) before entering sleep mode.
• To use the DMAC when in sleep mode, first exit sleep mode by means of an interrupt.
In cases when the CPU is not carrying out any other processing but is waiting for the DMAC
to end its transfer during DMAC operation, do not use the SLEEP instruction, but use the
transfer end flag bit (TE) in the channel DMA control register and a polling software loop.
7. Sampling of DREQ
If DREQ is set to level detection in DMA cycle-steal mode, sampling of DREQ may take place
before DACK is output. Note that some system configurations involve unnecessary DMA
transfers.
Operation:
As shown in Figure 9.25, sampling of DREQ is carried out immediately before the rising edge
of the third-state clock (CK) after completion of the bus cycle preceding the DMA bus cycle
where DACK is output.
If DACK is output after the third state of the DMA bus cycle, sampling of DREQ must be
carried out before DACK is output.
Number of states of
DMAC bus cycle
1
2
3
4
: DMAC bus cycle
Sampling point
Figure 9.25 DREQ Sampling Points
Rev. 7.00 Jan 31, 2006 page 221 of 658
REJ09B0272-0700