SH7032 Datasheet, PDF (126/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 7 Clock Pulse Generator (CPG)
7.3 Usage Notes
Board Design: When designing the board, place the crystal resonator and its load capacitors as
close as possible to the XTAL and EXTAL pins. Route no other signal lines near the XTAL and
EXTAL pin signal lines to prevent induction from interfering with correct oscillation. See figure
7.6.
No crossing
signal lines
C_L1
XTAL
C_L2
EXTAL
Figure 7.6 Precaution on Oscillator Circuit Board Design
Duty Cycle Correction Circuit: Duty cycle corrections are conducted for an input clock over 5
MHz. Duty cycles may not be corrected for a clock of under 5 MHz, but AC characteristics for the
high-level pulse width (t_CH) and low-level pulse width (t_CL) of the clock are satisfied, and the chip
will operate normally. Figure 7.7 shows the standard characteristics of duty cycle correction. This
duty cycle correction circuit is not for correcting transient fluctuations and jitter in the input clock.
Thus, it takes several tens of microseconds to obtain a stable clock after duty cycle correction is
performed.
Rev. 7.00 Jan 31, 2006 page 100 of 658
REJ09B0272-0700