SH7032 Datasheet, PDF (608/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix A On-Chip Supporting Module Registers
A.2.14 Timer Control Registers 0–4 (TCR0–TCR4)
ITU
Start Address: H'5FFFF04 (channel 0), H'5FFFF0E (channel 1), H'5FFFF18 (channel 2),
H'5FFFF22 (channel 3), H'5FFFF32 (channel 4)
Bus Width: 8
Bit
7
—
Initial value
*
Read/Write
—
Note: * Undetermined
6
CCLR1
0
R/W
5
CCLR0
0
R/W
4
CKEG1
0
R/W
3
CKEG0
0
R/W
2
TPSC2
0
R/W
1
TPSC1
0
R/W
0
TPSC0
0
R/W
Table A.15 TCR0–TCR4 Bit Functions
Bit Bit name
6,5 Counter clear 1, 0 (CCLR1,
CCLR0)
4,3 Clock edge 1, 0 (CKEG1,
CKEG0)
2–0 Timer prescaler 2–0
(TPSC2–TPSC0)
Note: * 0 or 1
Value
00
01
10
11
00
01
1*
00
00
01
01
10
10
11
11
Description
TCNT clear disabled
(Initial value)
TCNT cleared upon GRA compare match/input
capture
TCNT cleared upon GRB compare match/input
capture
Synchronized clear. TCNT cleared in synchronization
with counter clear of other timers operating in sync
Count on rising edge
(Initial value)
Count on falling edge
Count on both rising and falling edges
0 Internal clock: Count on φ
(Initial value)
1 Internal clock: Count on φ/2
0 Internal clock: Count on φ/4
1 Internal clock: Count on φ/8
0 External clock A: Count on TCLKA pin input
1 External clock B: Count on TCLKB pin input
0 External clock C: Count on TCLKC pin input
1 External clock D: Count on TCLKD pin input
Rev. 7.00 Jan 31, 2006 page 582 of 658
REJ09B0272-0700