SH7032 Datasheet, PDF (90/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 4 Exception Handling
4.7 Stack Status after Exception Handling
Table 4.10 shows the stack after exception handling.
Table 4.10 Stack after Exception Handling
Type
Address
error
Stack Status
Address of
SP instruction Upper 16 bits
after instruc-
tion that has
finished
executing
Lower 16 bits
SR Upper 16 bits
Lower 16 bits
Type
Interrupt
Stack Status
Address of
SP instruction Upper 16 bits
after instruc-
tion that
has finished
executing
Lower 16 bits
SR Upper 16 bits
Lower 16 bits
Trap
instruc-
tion
Address of
SP instruction Upper 16 bits
after TRAPA
instruction
Lower 16 bits
SR Upper 16 bits
Lower 16 bits
Illegal slot
instruc-
tion
SP
Branch
destination
address of
delayed
branch
instuction
SR
Upper 16 bits
Lower 16 bits
Upper 16 bits
Lower 16 bits
General
illegal
instruc-
SP
Start add-
ress of
Upper 16 bits
tion
illegal
instruction
Lower 16 bits
SR Upper 16 bits
Lower 16 bits
Note: Stack status is based on a bus width of 16 bits.
Rev. 7.00 Jan 31, 2006 page 64 of 658
REJ09BX0272-0700