SH7032 Datasheet, PDF (65/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Table 2.15 Shift Instructions
Instruction
ROTL Rn
ROTR Rn
ROTCL Rn
ROTCR Rn
SHAL Rn
SHAR Rn
SHLL Rn
SHLR Rn
SHLL2 Rn
SHLR2 Rn
SHLL8 Rn
SHLR8 Rn
SHLL16 Rn
SHLR16 Rn
Instruction Code
0100nnnn00000100
0100nnnn00000101
0100nnnn00100100
0100nnnn00100101
0100nnnn00100000
0100nnnn00100001
0100nnnn00000000
0100nnnn00000001
0100nnnn00001000
0100nnnn00001001
0100nnnn00011000
0100nnnn00011001
0100nnnn00101000
0100nnnn00101001
Operation
T ← Rn ← MSB
LSB → Rn → T
T ← Rn ← T
T → Rn → T
T ← Rn ← 0
MSB → Rn → T
T ← Rn ← 0
0 → Rn → T
Rn<<2 → Rn
Rn>>2 → Rn
Rn<<8 → Rn
Rn>>8 → Rn
Rn<<16 → Rn
Rn>>16 → Rn
Section 2 CPU
Execution Cycles
1
1
1
1
1
1
1
1
1
1
1
1
1
1
T Bit
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
—
—
—
—
—
—
Table 2.16 Branch Instructions
Instruction Instruction Code
Operation
Execution
Cycles
T Bit
BF label 10001011dddddddd If T = 0, disp × 2 + PC → PC; if T = 1, 3/1*
—
nop
BT label 10001001dddddddd If T = 1, disp × 2 + PC → PC; if T = 0, 3/1*
—
nop
BRA label 1010dddddddddddd Delayed branch, disp × 2 + PC → PC 2
—
BSR label 1011dddddddddddd Delayed branch, PC → PR, disp × 2 + 2
—
PC → PC
JMP @Rm 0100mmmm00101011 Delayed branch, Rm → PC
2
—
JSR @Rm 0100mmmm00001011 Delayed branch, PC → PR, Rm → PC 2
—
RTS
0000000000001011 Delayed branch, PR → PC
2
—
Note: * The execution state is three cycles when program branches, and one cycle when program
does not branch.
Rev. 7.00 Jan 31, 2006 page 39 of 658
REJ09B0272-0700