SH7032 Datasheet, PDF (595/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

A.2 Register Tables
Appendix A On-Chip Supporting Module Registers
A.2.1 Serial Mode Register (SMR)
SCI
Start Address: H'5FFFEC0 (channel 0), H'5FFFEC8 (channel 1)
Bus Width: 8/16
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
C/A CHR
PE
O/E STOP MP CKS1 CKS0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table A.3 SMR Bit Functions
Bit Bit name
Value* Description
7 Communication mode (C/A)
0
Asynchronous mode
(Initial value)
1
Synchronous mode
6 Character length (CHR)
0
8-bit data
(Initial value)
1
7-bit data
5 Parity enable (PE)
0
Parity bit addition and check disable
(Initial value)
1
Parity bit addition and check enable
4 Parity mode (O/E)
0
Even parity
(Initial value)
1
Odd parity
3 Stop bit length (STOP)
0
1 stop bit
(Initial value)
1
2 stop bits
2 Multiprocessor mode (MP)
0
Multiprocessor function disabled (Initial value)
1
Multiprocessor function selected
1,0 Clock select 1, 0 (CKS1, CKS0) 0
0 φ clock
(Initial value)
0
1 φ/4 clock
1
0 φ/16 clock
1
1 φ/64 clock
Note: * When 2 or more bits are treated as a group, the left side is the upper bit and the right the
lower bit.
Rev. 7.00 Jan 31, 2006 page 569 of 658
REJ09B0272-0700