SH7032 Datasheet, PDF (273/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
Bits 2–0—Timer Prescaler 2–0 (TPS2–TPS0): TPS2–TPS0 select the counter clock source.
When TPSC2 = 0 and an internal clock source is selected, the timer counts only falling edges.
When TPSC2 = 1 and an external clock is selected, the count edge is as set by CKEG1 and
CKEG0. When phase counting mode is selected for channel 2 (the MDF bit in the timer mode
register is 1), the settings of TPSC2–TPSC0 in TCR2 are ignored and the phase counting
operation takes priority.
Bit 2:
TPSC2
0
1
Bit 1:
TPSC1
0
1
0
1
Bit 0:
TPSC0
0
1
0
1
0
1
0
1
Counter Clock (and Cycle when φ = 10 MHz)
Internal clock φ
Internal clock φ/2
Internal clock φ/4
Internal clock φ/8
External clock A (TCLKA)
External clock B (TCLKB)
External clock C (TCLKC)
External clock D (TCLKD)
(Initial value)
10.2.10 Timer I/O Control Register (TIOR)
The timer I/O control register (TIOR) is an eight-bit read/write register that selects the output
compare or input capture function for general registers GRA and GRB. It also selects the function
of the TIOCA and TIOCB pins. If output compare is selected, TIOR also selects the output
settings. If input capture is selected, TIOR also selects the input capture edge. TIOR is initialized
to H'88 or H'08 by a reset and in standby mode. Each ITU channel has one TIOR.
Table 10.8 Timer I/O Control Register (TIOR)
Channel
0
1
2
3
4
Abbrevi-
ation
TIOR0
TIOR1
TIOR2
TIOR3
TIOR4
Function
TIOR controls the GRs. Some functions vary during PWM. When
channels 3 and 4 are set for complementary PWM mode/reset-
synchronized PWM mode, TIOR3 and TIOR4 settings are not valid.
Rev. 7.00 Jan 31, 2006 page 247 of 658
REJ09B0272-0700