SH7032 Datasheet, PDF (619/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix A On-Chip Supporting Module Registers
A.2.25 DMA Destination Address Registers 0–3 (DAR0–DAR3)
DMAC
Start Address: H'5FFFF44 (channel 0), H'5FFFF54 (channel 1), H'5FFFF64 (channel 2),
H'5FFFF74 (channel 3)
Bus Width: 16/32
Bit
31
30
29
28
27
26
25
24
Initial value
Read/Write
*
*
*
*
*
*
*
*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
23
22
21
20
19
18
17
16
Initial value
Read/Write
*
*
*
*
*
*
*
*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
15
14
13
12
11
10
9
8
Initial value
Read/Write
*
*
*
*
*
*
*
*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
7
6
5
4
3
2
1
0
Initial value
*
*
*
*
*
*
*
*
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: * Undetermined
Table A.26 DAR0–DAR3 Bit Functions
Bit
31–0
Bit name
(Specifies transfer destination
address)
Description
Specifies the address of the DMA transfer destination
Rev. 7.00 Jan 31, 2006 page 593 of 658
REJ09B0272-0700