SH7032 Datasheet, PDF (647/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix A On-Chip Supporting Module Registers
A.2.49 Refresh Timer Constant Register (RTCOR)
BSC
Start Address: H'5FFFFB2
Bus Width: 8/16/32 (read), 16 (write)
Bit
Initial value
Read/Write
15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W
Table A.50 RTCOR Bit Functions
Bit
Bit Name
7–0
(Compare match cycle)
Description
Set with compare match cycle
A.2.50 Timer Control/Status Register (TCSR)
Start Address: H'5FFFFB8
Bus Width: 8 (read), 16 (write)
Bit
7
6
5
4
OVF WT/IT TME
—
Initial value
0
0
0
1
Read/Write
R/(W)* R/W
R/W
—
Note: * Only 0 can be written, to clear the flag.
WDT
3
2
1
0
—
CKS2 CKS1 CKS0
1
0
0
0
—
R/W R/W R/W
Rev. 7.00 Jan 31, 2006 page 621 of 658
REJ09B0272-0700