SH7032 Datasheet, PDF (428/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Serial Communication Interface (SCI)
Receiving Serial Data (Synchronous Mode): Figure 13.18 shows a sample flowchart for
receiving serial data. When switching from asynchronous mode to synchronous mode, make sure
that ORER, PER, and FER are cleared to 0. If PER or FER is set to 1, the RDRF bit will not be set
and both transmitting and receiving will be disabled. Figure 13.19 shows an example of SCI
receive operation.
The procedure for receiving serial data is listed below.
1. SCI initialization: select the RxD pin function with the PFC.
2. Receive error handling and break detection: if a receive error occurs, read the ORER bit in
SSR to identify the error. After executing the necessary error handling, clear ORER to 0.
Transmitting/receiving cannot resume if ORER remains set to 1.
3. SCI status check and receive data read: read the serial status register (SSR), check that RDRF
is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0.
The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1.
4. To continue receiving serial data: read RDR, and clear RDRF to 0 before the frame MSB (bit
7) of the current frame is received. If the DMAC is started by a receive-data-full interrupt
(RXI) to read RDR, the RDRF bit is cleared automatically, so this step is unnecessary.
Rev. 7.00 Jan 31, 2006 page 402 of 658
REJ09B0272-0700