SH7032 Datasheet, PDF (111/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 6 User Break Controller (UBC)
6.1.3 Register Configuration
The user break controller has five registers as listed in table 6.1. These registers are used for
setting break conditions.
Table 6.1 User Break Controller Registers
Name
Abbr.
R/W Address*
Initial
Value Bus width
Break address register high
BARH R/W H'5FFFF90 H'0000 8, 16, 32
Break address register low
BARL R/W H'5FFFF92 H'0000 8, 16, 32
Break address mask register high
BAMRH R/W H'5FFFF94 H'0000 8, 16, 32
Break address mask register low
BAMRL R/W H'5FFFF96 H'0000 8, 16, 32
Break bus cycle register
BBR
R/W H'5FFFF98 H'0000 8, 16, 32
Note: * Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For details
on the register addresses, see section 8.3.5, Area Descriptions.
Rev. 7.00 Jan 31, 2006 page 85 of 658
REJ09B0272-0700