SH7032 Datasheet, PDF (10/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Item
Page
2.4.1 Instruction 37
Set by Classification
Table 2.13
Arithmetic
Instructions
2.4.2 Operation
Code Map
Table 2.18
Operation Code
Map
8.5.3 Wait State
Control
42, 43
151
10.4.5 Reset-
273
Synchronized PWM
Mode
Figure 10.31
Procedure for
Selecting Reset-
Synchronized PWM
Mode
10.4.6
276
Complementary
PWM Mode
Figure 10.33
Procedure for
Selecting
Complementary
PWM Mode
Revision (See Manual for Details)
Table amended
Instruction
Instruction Code
MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111
MULS Rm,Rn
0010nnnnmmmm1111
MULU Rm,Rn
0010nnnnmmmm1110
Operation
Signed operation of
(Rn) × (Rm) + MAC →
MAC
16 × 16 + 42 → 42-bit
Signed operation of
Rn × Rm → MAC
16 × 16 → 32-bit
Unsigned operation of
Rn × Rm → MAC
16 × 16 → 32-bit
Execution
Cycles
3/(2)*
1–3*
1–3*
T Bit
—
—
—
Table amended
Instruction Code
MSB
0000 0000 Fx
0000 Rn Fx
0110 Rn
Rm
Fx: 0000
LSB MD: 00
1001 NOP
1001
10MD SWAP.B
Rm,Rn
Fx: 0001
MD: 01
DIV0U
SWAP.W
Rm,Rn
Fx: 0010
MD: 10
Fx: 0011–1111
MD: 11
MOVT Rn
NEGC Rm,Rn NEG Rm,Rn
Description amended
Regardless of the state of the WAIT signal, when the RW1 bit, the
number of wait states selected by CBR refresh wait state insertion
bits 1 and 0 (RLW1, RLW0) in the refresh control register (RCR)
are inserted into the CAS-before-RAS refresh cycle.
Description of PFC setting added
Description of PFC setting added
Rev. 7. 00 Jan 31, 2006 page x of xxvi