SH7032 Datasheet, PDF (219/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 9 Direct Memory Access Controller (DMAC)
Start
Initial settings
(SAR, DAR, TCR, CHCR, DMAOR)
DE, DME = 1 and
No
NMIF, AE, TE = 0?
Yes
Transfer request
No
occurs?^*1
Yes
Transfer (1 transfer unit); TCR–1
→ TCR, SAR and DAR updated
*2
Bus mode,
transfer request mode,
*3 DREQ detection selection
system
TCR = 0?
No
Yes
DEI interrupt request
(when IE = 1)
Does
No NMIF = 1, AE = 1,
DE = 0, and DME
= 0?
Yes
Normal end Transfer ends
Does
NMIF = 1, AE = 1,
No
DE = 0, or DME
= 0?
Yes
Transfer aborted
Notes:
1. In auto-request mode, transfer begins when NMIF, AE, and TE are all 0 and the DE
and DME bits are set to 1.
2. DREQ = level detection in burst mode (external request), or cycle steal mode.
3. DREQ = edge detection in burst mode (external request), or auto request mode in
burst mode.
Figure 9.2 DMA Transfer Flowchart
Rev. 7.00 Jan 31, 2006 page 193 of 658
REJ09B0272-0700