SH7032 Datasheet, PDF (112/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 6 User Break Controller (UBC)
6.2 Register Descriptions
6.2.1 Break Address Registers (BAR)
There are two break address registers—break address register H (BARH) and break address
register L (BARL)—that together form a single group. Both are 16-bit read/write registers. BARH
stores the upper bits (bits 31–16) of the address of the break condition. BARL stores the lower bits
(bits 15–0) of the address of the break condition. A reset initializes both BARH and BARL to
H'0000. They are not initialized in standby mode.
BARH: Break address register H.
Bit
Initial value
Read/Write
15
BA31
0
R/W
14
BA30
0
R/W
13
BA29
0
R/W
12
BA28
0
R/W
11
BA27
0
R/W
10
BA26
0
R/W
9
BA25
0
R/W
8
BA24
0
R/W
Bit
Initial value
Read/Write
7
BA23
0
R/W
6
BA22
0
R/W
5
BA21
0
R/W
4
BA20
0
R/W
3
BA19
0
R/W
2
BA18
0
R/W
1
BA17
0
R/W
0
BA16
0
R/W
BARH Bits 15–0—Break Address 31–16 (BA31–BA16): BA31–BA16 store the upper bit values
(bits 31–16) of the address of the break condition.
BARL: Break address register L.
Bit
Initial value
Read/Write
15
14
13
12
11
10
9
8
BA15 BA14 BA13 BA12 BA11 BA10 BA9
BA8
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
BA7
BA6
BA5
BA4
BA3
BA2
BA1
BA0
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W
BARL Bits 15–0—Break Address 15–0 (BA15–BA0): BA15–BA0 store the lower bit values
(bits 15–0) of the address of the break condition.
Rev. 7.00 Jan 31, 2006 page 86 of 658
REJ09B0272-0700