SH7032 Datasheet, PDF (636/687 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix A On-Chip Supporting Module Registers
A.2.40 Bus Control Register (BCR)
BSC
Start Address: H'5FFFFA0
Bus Width: 8/16/32
Bit
15
14
13
12
11
10
9
8
DRAME IOE WARP RDDTY BAS
—
—
—
Initial value: 0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
—
—
—
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
Read/Write
—
—
—
—
—
—
—
—
Table A.41 BCR Bit Functions
Bit
Bit Name
15
DRAM enable (DRAME)
14
Multiplex I/O enable (IOE)
13
Warp mode (WARP)
12
RD duty (RDDTY)
11
Byte access select (BAS)
Value
0
1
0
1
0
1
0
1
0
1
Description
Area 1 is external memory space
(Initial value)
Area 1 is DRAM space
Area 6 is external memory space
(Initial value)
Area 6 is address/data multiplex I/O space
Normal mode: External access and internal
access not performed simultaneously
(Initial value)
Warp mode: External access and internal
access performed simultaneously
RD signal high width duty ratio is 50%
(Initial value)
RD signal high width duty ratio is 35%
WRH, WRL, and A0 signals valid
(Initial value)
WR, HBS, and LBS and signals valid
Rev. 7.00 Jan 31, 2006 page 610 of 658
REJ09B0272-0700